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5-Microstep Drive. Xilinx CPLD

Насколько я понял EPM3064 содержит 64 microsells. У Xilinx XC2C64A (тоже 64 ячейки) это легло в 33 ячейки или 52%.

На всякий случай вот распечатка всех деталей компиляции.

cpldfit: version L.33 Xilinx Inc.
Fitter Report
Design Name: uStep Date: 12-11-2009, 2:27PM
Device Used: XC2C64A-7-VQ44
Fitting Status: Successful

************************* Mapped Resource Summary **************************

Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
33 /64 ( 52%) 77 /224 ( 34%) 67 /160 ( 42%) 29 /64 ( 45%) 16 /33 ( 48%)

** Function Block Resources **

Function Mcells FB Inps Pterms IO CTC CTR CTS CTE
Block Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1 16/16* 28/40 37/56 2/ 8 1/1* 0/1 0/1 0/1
FB2 12/16 22/40 21/56 2/ 9 1/1* 0/1 0/1 0/1
FB3 3/16 6/40 8/56 3/ 9 1/1* 0/1 0/1 0/1
FB4 2/16 11/40 11/56 2/ 7 1/1* 0/1 0/1 0/1
----- ------- ------- ----- — — — —
Total 33/64 67/160 77/224 9/33 4/4 0/4 0/4 0/4

CTC - Control Term Clock
CTR - Control Term Reset
CTS - Control Term Set
CTE - Control Term Output Enable

* - Resource is exhausted

** Global Control Resources **

GCK GSR GTS DGE
Used/Tot Used/Tot Used/Tot Used/Tot
0/3 0/1 0/4 0/0

** Pin Resources **

End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************

** 9 Outputs **

Signal Total Total Bank Loc Pin Pin Pin I/O I/O Slew Reg Reg Init
Name Pts Inps No. Type Use STD Style Rate Use State
DUMP 3 6 2 FB1_12 31 GTS/I/O O LVCMOS33 OD SLOW DFF/S SET
A1 4 5 2 FB1_13 30 GSR/I/O O LVCMOS33 SLOW DFF RESET
OSCB 1 1 1 FB2_7 43 GCK/I/O O LVCMOS33 SLOW
STBY 1 3 1 FB2_13 3 I/O I/O LVCMOS33 OD/S FAST
A0 4 5 2 FB3_1 29 I/O O LVCMOS33 SLOW DFF RESET
B1 3 4 2 FB3_2 28 I/O O LVCMOS33 SLOW DFF RESET
B0 3 4 2 FB3_3 27 I/O O LVCMOS33 SLOW DFF RESET
BSIN 6 10 1 FB4_11 12 I/O O LVCMOS33 OD SLOW TFF/S SET
ASIN 6 10 1 FB4_13 13 I/O O LVCMOS33 OD SLOW TFF/S SET

** 24 Buried Nodes **

Signal Total Total Loc Reg Reg Init
Name Pts Inps Use State
QA<2> 5 9 FB1_1 TFF RESET
QA<1> 6 8 FB1_2 TFF RESET
QB<1> 3 4 FB1_3 DFF RESET
QB<5> 3 8 FB1_4 TFF RESET
QD<2> 3 14 FB1_5 TFF RESET
QD<1> 3 13 FB1_6 TFF RESET
QD<0> 3 12 FB1_7 TFF RESET
QB<6> 3 9 FB1_8 TFF RESET
QB<2> 3 5 FB1_9 DFF RESET
QB<3> 3 6 FB1_10 DFF RESET
QB<4> 3 7 FB1_11 TFF RESET
QB<7> 3 10 FB1_14 TFF RESET
Q11 3 7 FB1_15 DFF RESET
Q10 3 7 FB1_16 DFF RESET
QA<0> 3 5 FB2_3 TFF RESET
QC<0> 3 4 FB2_4 DFF RESET
N_PZ_175 2 4 FB2_8
QB<0> 2 3 FB2_9 DFF RESET
N_PZ_135 4 6 FB2_10
Q02 3 4 FB2_11 DEFF RESET
QC<1> 3 5 FB2_12 TFF RESET
Q05 2 3 FB2_14 DFF RESET
Q04 2 2 FB2_15 DFF RESET
Q03 2 2 FB2_16 DFF RESET

** 8 Inputs **

Signal Bank Loc Pin Pin Pin I/O I/O
Name No. Type Use STD Style
DIR 2 FB1_1 38 I/O I LVCMOS33 S
STP 2 FB1_2 37 I/O I LVCMOS33 S
RES 2 FB1_9 34 GTS/I/O I LVCMOS33 S
AIN 2 FB1_10 33 GTS/I/O I LVCMOS33 S
BIN 2 FB1_11 32 GTS/I/O I LVCMOS33 S
OSCA 1 FB2_6 42 I/O I LVCMOS33 S
CLK 1 FB2_12 2 I/O I LVCMOS33 S
STBY 1 FB2_13 3 I/O I/O LVCMOS33 S

Legend:
Pin No. - ~ - User Assigned
I/O Style - OD - OpenDrain

• PU - Pullup
• KPR - Keeper
• S - SchmittTrigger
• DG - DataGate
  Reg Use - LATCH - Transparent latch
• DFF - D-flip-flop
• DEFF - D-flip-flop with clock enable
• TFF - T-flip-flop
• TDFF - Dual-edge-triggered T-flip-flop
• DDFF - Dual-edge-triggered flip-flop
• DDEFF - Dual-edge-triggered flip-flop with clock enable
  /S (after any above flop/latch type) indicates initial state is Set
  ************************** Function Block Details ************************
  Legend:
  Total Pt - Total product terms used by the macrocell signal
  Loc - Location where logic was mapped in device
  Pin Type/Use - I - Input GCK - Global clock
  O - Output GTS - Global Output Enable
  (b) - Buried macrocell GSR - Global Set/Reset
  VRF - Vref
  Pin No. - ~ - User Assigned
  *********************************** FB1 ***********************************
  This function block is part of I/O Bank number: 2
  Number of function block inputs used/remaining: 28/12
  Number of function block control terms used/remaining: 1/3
  Number of PLA product terms used/remaining: 37/19
  Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
  Name Pt No. Type Use
  QA<2> 5 FB1_1 38 I/O I +
  QA<1> 6 FB1_2 37 I/O I +
  QB<1> 3 FB1_3 36 I/O (b) +
  QB<5> 3 FB1_4 (b) (b) +
  QD<2> 3 FB1_5 (b) (b) +
  QD<1> 3 FB1_6 (b) (b) +
  QD<0> 3 FB1_7 (b) (b) +
  QB<6> 3 FB1_8 (b) (b) +
  QB<2> 3 FB1_9 34 GTS/I/O I +
  QB<3> 3 FB1_10 33 GTS/I/O I +
  QB<4> 3 FB1_11 32 GTS/I/O I +
  DUMP 3 FB1_12 31 GTS/I/O O +
  A1 4 FB1_13 30 GSR/I/O O +
  QB<7> 3 FB1_14 (b) (b) +
  Q11 3 FB1_15 (b) (b) +
  Q10 3 FB1_16 (b) (b) +

Signals Used by Logic in Function Block
1: AIN 11: QA<1> 20: QB<7>
2: BIN 12: QA<2> 21: QC<0>
3: CLK 13: QB<0> 22: QC<1>
4: N_PZ_135 14: QB<1> 23: QD<0>
5: N_PZ_175 15: QB<2> 24: QD<1>
6: Q02 16: QB<3> 25: QD<2>
7: Q05 17: QB<4> 26: RES
8: Q10 18: QB<5> 27: STBY
9: Q11 19: QB<6> 28: STBY.PIN
10: QA<0>

Signal 1 2 3 4 FB
Name 0----±—0----±—0----±—0----±—0 Inputs
QA<2> …XX.XX…XXX…X…X… 9
QA<1> …XX.XX…XX…X…X… 8
QB<1> …XX…XX… 4
QB<5> …XX…XXXXXX… 8
QD<2> …X…X…XXXXXXXX…XXX.X… 14
QD<1> …X…X…XXXXXXXX…XX…X… 13
QD<0> …X…X…XXXXXXXX…X…X… 12
QB<6> …XX…XXXXXXX… 9
QB<2> …XX…XXX… 5
QB<3> …XX…XXXX… 6
QB<4> …XX…XXXXX… 7
DUMP …X…XXXX…X… 6
A1 …X.X…X…XX… 5
QB<7> …XX…XXXXXXXX… 10
Q11 .XX…X…XXXX… 7
Q10 X.X…X…XXXX… 7
0----±—1----±—2----±—3----±—4
0 0 0 0
*********************************** FB2 ***********************************
This function block is part of I/O Bank number: 1
Number of function block inputs used/remaining: 22/18
Number of function block control terms used/remaining: 1/3
Number of PLA product terms used/remaining: 21/35
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB2_1 39 I/O
(unused) 0 FB2_2 40 I/O
QA<0> 3 FB2_3 (b) (b) +
QC<0> 3 FB2_4 (b) (b) +
(unused) 0 FB2_5 41 I/O
(unused) 0 FB2_6 42 I/O I
OSCB 1 FB2_7 43 GCK/I/O O
N_PZ_175 2 FB2_8 44 GCK/I/O (b)
QB<0> 2 FB2_9 (b) (b) +
N_PZ_135 4 FB2_10 1 GCK/I/O (b)
Q02 3 FB2_11 (b) (b) +
QC<1> 3 FB2_12 2 I/O I +
STBY 1 FB2_13 3 I/O I/O
Q05 2 FB2_14 (b) (b) +
Q04 2 FB2_15 (b) (b) +
Q03 2 FB2_16 (b) (b) +

Signals Used by Logic in Function Block
1: CLK 9: QA<0> 16: QC<1>
2: DIR 10: QA<1> 17: QD<0>
3: N_PZ_135 11: QA<2> 18: QD<1>
4: OSCA 12: QB<0> 19: QD<2>
5: Q02 13: QB<6> 20: RES
6: Q03 14: QB<7> 21: STBY.PIN
7: Q04 15: QC<0> 22: STP
8: Q05

Signal 1 2 3 4 FB
Name 0----±—0----±—0----±—0----±—0 Inputs
QA<0> X.X…XX…X… 5
QC<0> X.X…X…X… 4
OSCB …X… 1
N_PZ_175 …XX…XX… 4
QB<0> X.X…X… 3
N_PZ_135 …X…XXXX…X… 6
Q02 XX…XX… 4
QC<1> X.X…X…X…X… 5
STBY …XXX… 3
Q05 X…XX… 3
Q04 X…X… 2
Q03 X…X… 2
0----±—1----±—2----±—3----±—4
0 0 0 0
*********************************** FB3 ***********************************
This function block is part of I/O Bank number: 2
Number of function block inputs used/remaining: 6/34
Number of function block control terms used/remaining: 1/3
Number of PLA product terms used/remaining: 8/48
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
A0 4 FB3_1 29 I/O O +
B1 3 FB3_2 28 I/O O +
B0 3 FB3_3 27 I/O O +
(unused) 0 FB3_4 (b)
(unused) 0 FB3_5 (b)
(unused) 0 FB3_6 23 I/O
(unused) 0 FB3_7 (b)
(unused) 0 FB3_8 (b)
(unused) 0 FB3_9 (b)
(unused) 0 FB3_10 22 I/O
(unused) 0 FB3_11 21 I/O
(unused) 0 FB3_12 20 I/O
(unused) 0 FB3_13 (b)
(unused) 0 FB3_14 19 I/O
(unused) 0 FB3_15 18 I/O
(unused) 0 FB3_16 (b)

Signals Used by Logic in Function Block
1: CLK 3: Q10 5: QC<0>
2: N_PZ_175 4: Q11 6: QC<1>

Signal 1 2 3 4 FB
Name 0----±—0----±—0----±—0----±—0 Inputs
A0 XXX.XX… 5
B1 XX.X.X… 4
B0 XX.X.X… 4
0----±—1----±—2----±—3----±—4
0 0 0 0
*********************************** FB4 ***********************************
This function block is part of I/O Bank number: 1
Number of function block inputs used/remaining: 11/29
Number of function block control terms used/remaining: 1/3
Number of PLA product terms used/remaining: 11/45
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB4_1 5 I/O
(unused) 0 FB4_2 6 I/O
(unused) 0 FB4_3 (b)
(unused) 0 FB4_4 (b)
(unused) 0 FB4_5 (b)
(unused) 0 FB4_6 (b)
(unused) 0 FB4_7 8 I/O
(unused) 0 FB4_8 (b)
(unused) 0 FB4_9 (b)
(unused) 0 FB4_10 (b)
BSIN 6 FB4_11 12 I/O O +
(unused) 0 FB4_12 (b)
ASIN 6 FB4_13 13 I/O O +
(unused) 0 FB4_14 14 I/O
(unused) 0 FB4_15 16 I/O
(unused) 0 FB4_16 (b)

Signals Used by Logic in Function Block
1: ASIN 5: QA<1> 9: QB<2>
2: BSIN 6: QA<2> 10: QB<3>
3: CLK 7: QB<0> 11: QB<4>
4: QA<0> 8: QB<1>

Signal 1 2 3 4 FB
Name 0----±—0----±—0----±—0----±—0 Inputs
BSIN .XXXXXXXXXX… 10
ASIN X.XXXXXXXXX… 10
0----±—1----±—2----±—3----±—4
0 0 0 0
******************************* Equations ********************************

********** Mapped Logic **********

FDCPE_A0: FDCPE port map (A0,A0_D,CLK,‘0’,‘0’,‘1’);
A0_D <= (QC(0) AND N_PZ_175)
XOR ((N_PZ_175 AND QC(1) AND NOT Q10)
OR (N_PZ_175 AND NOT QC(1) AND Q10));

FDCPE_A1: FDCPE port map (A1,A1_D,CLK,‘0’,‘0’,‘1’);
A1_D <= (QC(0) AND N_PZ_175)
XOR ((N_PZ_175 AND QC(1) AND Q10)
OR (N_PZ_175 AND NOT QC(1) AND NOT Q10));

FTCPE_ASIN: FTCPE port map (ASIN,ASIN_T,CLK,‘0’,‘0’,‘1’);
ASIN_T <= ((NOT QA(1) AND NOT QA(0) AND QA(2) AND QB(0) AND QB(2) AND ASIN)
OR (NOT QB(4) AND NOT QB(1) AND NOT QB(0) AND NOT QB(2) AND NOT QB(3) AND NOT ASIN)
OR (QA(1) AND QA(0) AND NOT QA(2) AND QB(1) AND QB(0) AND QB(2) AND
QB(3) AND ASIN)
OR (QA(1) AND NOT QA(0) AND NOT QA(2) AND QB(4) AND QB(1) AND QB(0) AND
QB(2) AND ASIN)
OR (NOT QA(1) AND QA(0) AND NOT QA(2) AND QB(4) AND QB(0) AND QB(2) AND
QB(3) AND ASIN)); – Open Drain

FDCPE_B0: FDCPE port map (B0,B0_D,CLK,‘0’,‘0’,‘1’);
B0_D <= ((N_PZ_175 AND QC(1) AND NOT Q11)
OR (N_PZ_175 AND NOT QC(1) AND Q11));

FDCPE_B1: FDCPE port map (B1,B1_D,CLK,‘0’,‘0’,‘1’);
B1_D <= ((N_PZ_175 AND QC(1) AND Q11)
OR (N_PZ_175 AND NOT QC(1) AND NOT Q11));

FTCPE_BSIN: FTCPE port map (BSIN,BSIN_T,CLK,‘0’,‘0’,‘1’);
BSIN_T <= ((NOT QA(1) AND NOT QA(0) AND NOT QA(2) AND QB(0) AND QB(2) AND BSIN)
OR (NOT QB(4) AND NOT QB(1) AND NOT QB(0) AND NOT QB(2) AND NOT QB(3) AND NOT BSIN)
OR (NOT QA(1) AND NOT QA(2) AND QB(1) AND QB(0) AND QB(2) AND QB(3) AND
BSIN)
OR (NOT QA(0) AND NOT QA(2) AND QB(4) AND QB(1) AND QB(0) AND QB(2) AND
BSIN)
OR (QA(1) AND QA(0) AND NOT QA(2) AND QB(4) AND QB(0) AND QB(2) AND
QB(3) AND BSIN)); – Open Drain

FDCPE_DUMP: FDCPE port map (DUMP,DUMP_D,CLK,‘0’,‘0’,‘1’);
DUMP_D <= NOT (((NOT STBY.PIN)
OR (QB(6) AND QB(4) AND QB(5) AND QB(7)))); – Open Drain

N_PZ_135 <= ((QC(0) AND Q05 AND NOT Q02 AND QA(2))
OR (NOT QC(0) AND Q05 AND Q02 AND QA(2))
OR (QC(0) AND NOT QA(1) AND NOT QA(0) AND Q05 AND Q02 AND NOT QA(2))
OR (NOT QC(0) AND NOT QA(1) AND NOT QA(0) AND Q05 AND NOT Q02 AND NOT QA(2)));

N_PZ_175 <= ((RES AND NOT STBY.PIN)
OR (RES AND NOT QB(6) AND NOT QB(7)));

OSCB <= NOT OSCA;

FDCPE_Q02: FDCPE port map (Q02,NOT DIR,CLK,‘0’,‘0’,Q02_CE);
Q02_CE <= (Q03 AND NOT Q04);

FDCPE_Q03: FDCPE port map (Q03,NOT STP,CLK,‘0’,‘0’,‘1’);

FDCPE_Q04: FDCPE port map (Q04,Q03,CLK,‘0’,‘0’,‘1’);

FDCPE_Q05: FDCPE port map (Q05,Q05_D,CLK,‘0’,‘0’,‘1’);
Q05_D <= (Q03 AND NOT Q04);

FDCPE_Q10: FDCPE port map (Q10,Q10_D,CLK,‘0’,‘0’,‘1’);
Q10_D <= NOT (((NOT Q10 AND AIN)
OR (QB(6) AND QB(4) AND QB(5) AND QB(7))));

FDCPE_Q11: FDCPE port map (Q11,Q11_D,CLK,‘0’,‘0’,‘1’);
Q11_D <= NOT (((NOT Q11 AND BIN)
OR (QB(6) AND QB(4) AND QB(5) AND QB(7))));

FTCPE_QA0: FTCPE port map (QA(0),QA_T(0),CLK,‘0’,‘0’,‘1’);
QA_T(0) <= ((NOT RES AND QA(0))
OR (RES AND NOT N_PZ_135 AND Q05));

FTCPE_QA1: FTCPE port map (QA(1),QA_T(1),CLK,‘0’,‘0’,‘1’);
QA_T(1) <= ((NOT RES AND QA(1))
OR (QC(0) AND RES AND NOT N_PZ_135 AND QA(0) AND Q05 AND NOT Q02)
OR (QC(0) AND RES AND NOT N_PZ_135 AND NOT QA(0) AND Q05 AND Q02)
OR (NOT QC(0) AND RES AND NOT N_PZ_135 AND QA(0) AND Q05 AND Q02)
OR (NOT QC(0) AND RES AND NOT N_PZ_135 AND NOT QA(0) AND Q05 AND NOT Q02));

FTCPE_QA2: FTCPE port map (QA(2),QA_T(2),CLK,‘0’,‘0’,‘1’);
QA_T(2) <= ((NOT RES AND QA(2))
OR (NOT N_PZ_135 AND NOT QA(1) AND NOT QA(0) AND Q05 AND QA(2))
OR (QC(0) AND RES AND NOT N_PZ_135 AND QA(1) AND QA(0) AND Q05 AND
NOT Q02)
OR (NOT QC(0) AND RES AND NOT N_PZ_135 AND QA(1) AND QA(0) AND Q05 AND
Q02));

FDCPE_QB0: FDCPE port map (QB(0),QB_D(0),CLK,‘0’,‘0’,‘1’);
QB_D(0) <= (NOT N_PZ_135 AND NOT QB(0));

FDCPE_QB1: FDCPE port map (QB(1),QB_D(1),CLK,‘0’,‘0’,‘1’);
QB_D(1) <= ((NOT N_PZ_135 AND QB(1) AND NOT QB(0))
OR (NOT N_PZ_135 AND NOT QB(1) AND QB(0)));

FDCPE_QB2: FDCPE port map (QB(2),QB_D(2),CLK,‘0’,‘0’,‘1’);
QB_D(2) <= (NOT N_PZ_135 AND QB(2))
XOR (NOT N_PZ_135 AND QB(1) AND QB(0));

FDCPE_QB3: FDCPE port map (QB(3),QB_D(3),CLK,‘0’,‘0’,‘1’);
QB_D(3) <= (NOT N_PZ_135 AND QB(3))
XOR (NOT N_PZ_135 AND QB(1) AND QB(0) AND QB(2));

FTCPE_QB4: FTCPE port map (QB(4),QB_T(4),CLK,‘0’,‘0’,‘1’);
QB_T(4) <= ((N_PZ_135 AND QB(4))
OR (NOT N_PZ_135 AND QB(1) AND QB(0) AND QB(2) AND QB(3)));

FTCPE_QB5: FTCPE port map (QB(5),QB_T(5),CLK,‘0’,‘0’,‘1’);
QB_T(5) <= ((N_PZ_135 AND QB(5))
OR (NOT N_PZ_135 AND QB(4) AND QB(1) AND QB(0) AND QB(2) AND
QB(3)));

FTCPE_QB6: FTCPE port map (QB(6),QB_T(6),CLK,‘0’,‘0’,‘1’);
QB_T(6) <= ((N_PZ_135 AND QB(6))
OR (NOT N_PZ_135 AND QB(4) AND QB(1) AND QB(0) AND QB(2) AND
QB(3) AND QB(5)));

FTCPE_QB7: FTCPE port map (QB(7),QB_T(7),CLK,‘0’,‘0’,‘1’);
QB_T(7) <= ((N_PZ_135 AND QB(7))
OR (NOT N_PZ_135 AND QB(6) AND QB(4) AND QB(1) AND QB(0) AND
QB(2) AND QB(3) AND QB(5)));

FDCPE_QC0: FDCPE port map (QC(0),QC_D(0),CLK,‘0’,‘0’,‘1’);
QC_D(0) <= ((QC(0) AND RES AND NOT N_PZ_135)
OR (NOT QC(0) AND RES AND N_PZ_135));

FTCPE_QC1: FTCPE port map (QC(1),QC_T(1),CLK,‘0’,‘0’,‘1’);
QC_T(1) <= ((NOT RES AND QC(1))
OR (RES AND N_PZ_135 AND NOT QA(2)));

FTCPE_QD0: FTCPE port map (QD(0),QD_T(0),CLK,‘0’,‘0’,‘1’);
QD_T(0) <= ((Q05 AND QD(0))
OR (NOT Q05 AND QB(6) AND QB(4) AND QB(1) AND QB(0) AND QB(2) AND
QB(3) AND QB(5) AND QB(7) AND STBY));

FTCPE_QD1: FTCPE port map (QD(1),QD_T(1),CLK,‘0’,‘0’,‘1’);
QD_T(1) <= ((Q05 AND QD(1))
OR (NOT Q05 AND QB(6) AND QB(4) AND QB(1) AND QB(0) AND QB(2) AND
QB(3) AND QB(5) AND QB(7) AND QD(0) AND STBY));

FTCPE_QD2: FTCPE port map (QD(2),QD_T(2),CLK,‘0’,‘0’,‘1’);
QD_T(2) <= ((Q05 AND QD(2))
OR (NOT Q05 AND QB(6) AND QB(4) AND QB(1) AND QB(0) AND QB(2) AND
QB(3) AND QB(5) AND QB(7) AND QD(0) AND STBY AND QD(1)));

STBY <= NOT ((QD(0) AND QD(1) AND QD(2))); – Open Drain

Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FDDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
FTDCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);

****************************** Device Pin Out *****************************

Device : XC2C64A-7-VQ44

--------------------------------
/44 43 42 41 40 39 38 37 36 35 34 \
| 1 33 |
| 2 32 |
| 3 31 |
| 4 30 |
| 5 XC2C64A-7-VQ44 29 |
| 6 28 |
| 7 27 |
| 8 26 |
| 9 25 |
| 10 24 |
| 11 23 |
\ 12 13 14 15 16 17 18 19 20 21 22 /
--------------------------------

Pin Signal Pin Signal
No. Name No. Name
1 KPR 23 KPR
2 CLK 24 TDO
3 STBY 25 GND
4 GND 26 VCCIO-3.3
5 KPR 27 B0
6 KPR 28 B1
7 VCCIO-3.3 29 A0
8 KPR 30 A1
9 TDI 31 DUMP
10 TMS 32 BIN
11 TCK 33 AIN
12 BSIN 34 RES
13 ASIN 35 VCCAUX
14 KPR 36 KPR
15 VCC 37 STP
16 KPR 38 DIR
17 GND 39 KPR
18 KPR 40 KPR
19 KPR 41 KPR
20 KPR 42 OSCA
21 KPR 43 OSCB
22 KPR 44 KPR

Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
KPR = Unused I/O with weak keeper (leave unconnected)
WPU = Unused I/O with weak pull up (leave unconnected)
TIE = Unused I/O floating – must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
VCCAUX = Power supply for JTAG pins
VCCIO-3.3 = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
VCCIO-2.5 = I/O supply voltage for LVCMOS25, SSTL2_I
VCCIO-1.8 = I/O supply voltage for LVCMOS18
VCCIO-1.5 = I/O supply voltage for LVCMOS15, HSTL_I
VREF = Reference voltage for indicated input standard
*VREF = Reference voltage pin selected by software
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified : xc2c64a-7-VQ44
Optimization Method : DENSITY
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Set Unused I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Enable Input Registers : ON
Function Block Fan-in Limit : 38
Use DATA_GATE Attribute : ON
Set Tristate Outputs to Termination Mode : KEEPER
Default Voltage Standard for All Outputs : LVCMOS18
Input Limit : 32
Pterm Limit : 28

Что-то не могу разобраться как в ISE Project Navigator запускать симулятор (кажись wave называется).

Ткните пожалуйста пальцем куда смотреть надо и в какой последовательности.

НЕМНОГО теории Верилога, и присланный проект компилится без ошибок.
Лег в EPM3064, занял 64% - как будет работать посмотрим на праздниках.

А где то можно глянуть ?

А где то можно глянуть ?

***** Project compilation was successful

** DEVICE SUMMARY **

Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized

ustep EPM3064ALC44-4 7 8 1 41 13 64 %

User Pins: 7 8 1

Project Information c:\maxplus2\maxwork\g900m\ustep.rpt

** AUTO GLOBAL SIGNALS **

INFO: Signal ‘CLK’ chosen for auto global Clock

Project Information c:\maxplus2\maxwork\g900m\ustep.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

Actual
User Assignments
Assignments (if different) Node Name

ustep@4 AIN
ustep@40 ASIN
ustep@8 A0
ustep@9 A1
ustep@5 BIN
ustep@11 BSIN
ustep@12 B0
ustep@14 B1
ustep@43 CLK
ustep@6 DIR
ustep@16 DUMP
ustep@2 OSCA
ustep@18 OSCB
ustep@1 RES
ustep@19 STBY
ustep@41 STP

Project Information c:\maxplus2\maxwork\g900m\ustep.rpt

***** Project compilation was successful

Project Information c:\maxplus2\maxwork\g900m\ustep.rpt

а сам проект глянуть можно ? 😃

>> а сам проект глянуть можно ? 😃 Если Автор не против, то можно.

А прочитать первое сообщение в этой теме слабо? Там кстати и код выложен один к одному как я Юрию переслал.

Для самых ленивых код ниже.
Юрий, обратите внимание на STBY. Тут он несколько по другому сформирован. Вы не пробовали смотреть на STBY and DUMP в симуляции. Каждые 400us что-то выдается на STBY или код еще сыроват, хоть и работает?

Вместо смайликов надо подставить B )
Пробела между ними не должно быть.

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Oleg
//
// Create Date: 09:45:02 11/04/2009
// Design Name:
// Module Name: uStep
// Project Name:
// Target Devices: XC2C64A-7VQ44C
// Tool versions:
// Description: 80V 8A Stepper Motor Drive
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uStep(
input CLK, AIN, BIN, DIR, STP, OSCA, RES,
inout STBY,
output ASIN, BSIN, DUMP, A0, A1, B0, B1, OSCB-);
wire [2:0] QA;
wire [7:0] QB;
wire [1:0] QC;
wire [2:0] QD;
//T_BASE--------------------------------------------------------------------------
CB8R C03 (.C(CLK), .R(G14), .Q(QB-));
DF F12 (.C(CLK), .D(G24), .R(0), .CE(1), .S(~STBY), .Q(Q12));
assign DUMP = ~Q12 ? 1’bz : 1’b0;
assign G24 = QB[7] & QB[6] & QB[5] & QB[4];
assign OSCB = ~OSCA;
//PH_GEN--------------------------------------------------------------------------
DF F02 (.C(CLK), .D(~DIR), .R(0), .S(0), .CE(G16), .Q(Q02));
DF F03 (.C(CLK), .D(~STP), .R(0), .S(0), .CE(1), .Q(Q03));
DF F04 (.C(CLK), .D(Q03), .R(0), .S(0), .CE(1), .Q(Q04));
DF F05 (.C(CLK), .D(G16), .R(0), .S(0), .CE(1), .Q(Q05));
CB2BRE C00 (.C(CLK), .UD(Q02), .R(~RES), .CE(G14), .Q(QC));
CB3BRE C01 (.C(CLK), .UD(G13), .R(~RES), .CE(G15), .Q(QA));
CB3RE C02 (.C(CLK), .R(Q05), .CE(G18), .Q(QD));
assign G12 = QC[1] ^ QC[0];
assign G13 = QC[0] ^ Q02;
assign G11 = ( G13 & QA[2]) | (~G13 & ~QA[2] & ~QA[1] & ~QA[0]);
assign G14 = G11 & Q05;
assign G15 = ~G11 & Q05;
assign G16 = Q03 & ~Q04;
assign G17 = QD[2] & QD[1] & QD[0];
assign STBY = G17 ? 1’bz : 1’b0; //assign STBY = ~G17 ? 1’bz : 1’b0;
assign G18 = ~G17 & QB[7] & QB[6] & QB[5] & QB[4] & QB[3] &QB[2] & QB[1] & QB[0];
//SIN_COS-------------------------------------------------------------------------
DF F00 (.C(CLK), .D(G00), .R(G05), .S(0), .CE(1), .Q(Q00));
DF F01 (.C(CLK), .D(G10), .R(G05), .S(0), .CE(1), .Q(Q01));
assign G01 = QA[2] & ~QA[1] & ~QA[0] & QB[2] & QB[0];
assign G02 = ~QA[2] & QA[1] & QA[0] & QB[3] & QB[2] & QB[1] & QB[0];
assign G03 = ~QA[2] & QA[1] & ~QA[0] & QB[4] & QB[2] & QB[1] & QB[0];
assign G04 = ~QA[2] & ~QA[1] & QA[0] & QB[4] & QB[3] & QB[2] & QB[0];
assign G06 = ~QA[2] & ~QA[1] & ~QA[0] & QB[2] & QB[0];
assign G07 = ~QA[2] & ~QA[1] & QA[0] & QB[3] & QB[2] & QB[1] & QB[0];
assign G08 = ~QA[2] & QA[1] & ~QA[0] & QB[4] & QB[2] & QB[1] & QB[0];
assign G09 = ~QA[2] & QA[1] & QA[0] & QB[4] & QB[3] & QB[2] & QB[0];
assign G00 = Q00 | G01 | G02 | G03 | G04;
assign G10 = Q01 | G06 | G07 | G08 | G09;
assign G05 = ~QB[4] & ~QB[3] & ~QB[2] & ~QB[1] & ~QB[0];
assign BSIN = ~Q01 ? 1’bz : 1’b0;
assign ASIN = ~Q00 ? 1’bz : 1’b0;
//PH_DRV----------------------------------------
DF F06 (.C(CLK), .D(G20), .R(G19), .S(0), .CE(1), .Q(A0));
DF F07 (.C(CLK), .D(~G20), .R(G19), .S(0), .CE(1), .Q(A1));
DF F08 (.C(CLK), .D(G22), .R(G19), .S(0), .CE(1), .Q(B0));
DF F09 (.C(CLK), .D(~G22), .R(G19), .S(0), .CE(1), .Q(B1));
DF F10 (.C(CLK), .D(G21), .R(G24), .S(0), .CE(1), .Q(Q10));
DF F11 (.C(CLK), .D(G23), .R(G24), .S(0), .CE(1), .Q(Q11));
assign G19 = ~RES | (STBY & (QB[7] | QB[6]));
assign G22 = Q11 ^ QC[1]; //assign G22 = Q11 ^ QD[1];
assign G23 = Q11 | ~BIN;
assign G20 = Q10 ^ G12;
assign G21 = Q10 | ~AIN;
//the rest of the main module code here:
endmodule
/////////////////////////////////////////////////////////////////////////////////-
module DF (input D, C, CE, R, S, output Q);
reg df = 0;
always @(posedge C)
if ®
df <= 1’h0;
else if (S)
df <= 1’b1;
else if (CE)
df <= D;
assign Q = df;
endmodule
/////////////////////////////////////////////////////////////////////////////////-
module CB8R (input C, R, output [7:0] Q);
reg [7:0] count = 0;
always @(posedge C)
if ®
count <= 0;
else
count <= count + 1;
assign Q = count;
endmodule
/////////////////////////////////////////////////////////////////////////////////-
module CB2BRE (input UD, R, CE, C, output [1:0] Q);
reg [1:0] u_d = 0;
always @(posedge C)
if ®
u_d <= 0;
else if (CE)
if (UD) begin
u_d <= u_d + 1;
end
else begin
u_d <= u_d - 1;
end
assign Q = u_d;
endmodule
//////////////////////////////////////////////my add///////////////////////////////////-
module CB3BRE (input UD, R, CE, C, output [2:0] Q);
reg [2:0] u_d = 0;
always @(posedge C)
if ®
u_d <= 0;
else if (CE)
if (UD) begin
u_d <= u_d + 1;
end
else begin
u_d <= u_d - 1;
end
assign Q = u_d;
endmodule
////////////////////////////////////////corrected output [7:0]/////////////////////////////////////////-
module CB3RE (input C, R, CE, output [2:0] Q);
reg [2:0] count = 0;
always @(posedge C)
if ®
count <= 0;
else if (CE)
count <= count + 1;
assign Q = count;
endmodule
/////////////////////////////////////////////////////////////////////////////////-

А прочитать первое сообщение в этой теме слабо? Там кстати и код выложен один к одному как я Юрию переслал.

Я вообще то про проект на Алтере а не на Ксилинке. Товарищ писал что это ему удалось.
>>Марисс не возражает
😎

Вот это компилится Максом.
//`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Oleg
//
// Create Date: 09:45:02 11/04/2009
// Design Name:
// Module Name: uStep
// Project Name:
// Target Devices: XC2C64A-7VQ44C
// Tool versions:
// Description: 80V 8A Stepper Motor Driver
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uStep(CLK, AIN, BIN, DIR, STP, OSCA, RES,
STBY,
ASIN, BSIN, DUMP, A0, A1, B0, B1, OSCB-);

input CLK, AIN, BIN, DIR, STP, OSCA, RES;
inout STBY;
output ASIN, BSIN, DUMP, A0, A1, B0, B1, OSCB;
wire [2:0] QA;
wire [7:0] QB;
wire [1:0] QC;
wire [2:0] QD;
wire G01,G02,G03,G04,G05,G06,G07,G08,G09;
wire G11,G12;
wire G17;
//T_BASE--------------------------------------------------------------------------
CB8R C03 (.C(CLK), .R(G14), .Q(QB-));
DF F12 (.C(CLK), .D(G24), .R(0), .CE(1), .S(~STBY), .Q(Q12));
assign DUMP = ~Q12 ? 1’bz : 1’b0;
assign G24 = QB[7] & QB[6] & QB[5] & QB[4];
assign OSCB = ~OSCA;
//PH_GEN--------------------------------------------------------------------------
DF F02 (.C(CLK), .D(DIR), .R(0), .S(0), .CE(G16), .Q(Q02));
DF F03 (.C(CLK), .D(STP), .R(0), .S(0), .CE(1), .Q(Q03));
DF F04 (.C(CLK), .D(Q03), .R(0), .S(0), .CE(1), .Q(Q04));
DF F05 (.C(CLK), .D(G16), .R(0), .S(0), .CE(1), .Q(Q05));
CB2BRE C00 (.C(CLK), .UD(Q02), .R(~RES), .CE(G14), .Q(QC));
CB3BRE C01 (.C(CLK), .UD(G13), .R(~RES), .CE(G15), .Q(QA));
CB3RE C02 (.C(CLK), .R(Q05), .CE(G18), .Q(QD));
assign G12 = QC[1] ^ QC[0];
assign G13 = QC[0] ^ Q02;
assign G11 = ( G13 & QA[2]) | (~G13 & ~QA[2] & ~QA[1] & ~QA[0]);
assign G14 = G11 & Q05;
assign G15 = ~G11 & Q05;
assign G16 = Q03 & ~Q04;
assign G17 = QD[2] & QD[1] & QD[0];
assign STBY = ~G17 ? 1’bz : 1’b0;
assign G18 = ~G17 & QB[7] & QB[6] & QB[5] & QB[4] & QB[3] &QB[2] & QB[1] & QB[0];
//SIN_COS-------------------------------------------------------------------------
DF F00 (.C(CLK), .D(G00), .R(G05), .S(0), .CE(1), .Q(Q00));
DF F01 (.C(CLK), .D(G10), .R(G05), .S(0), .CE(1), .Q(Q01));
assign G01 = QA[2] & ~QA[1] & ~QA[0] & QB[2] & QB[0];
assign G02 = ~QA[2] & QA[1] & QA[0] & QB[3] & QB[2] & QB[1] & QB[0];
assign G03 = ~QA[2] & QA[1] & ~QA[0] & QB[4] & QB[2] & QB[1] & QB[0];
assign G04 = ~QA[2] & ~QA[1] & QA[0] & QB[4] & QB[3] & QB[2] & QB[0];
assign G06 = ~QA[2] & ~QA[1] & ~QA[0] & QB[2] & QB[0];
assign G07 = ~QA[2] & ~QA[1] & QA[0] & QB[3] & QB[2] & QB[1] & QB[0];
assign G08 = ~QA[2] & QA[1] & ~QA[0] & QB[4] & QB[2] & QB[1] & QB[0];
assign G09 = ~QA[2] & QA[1] & QA[0] & QB[4] & QB[3] & QB[2] & QB[0];
assign G00 = Q00 | G01 | G02 | G03 | G04;
assign G10 = Q01 | G06 | G07 | G08 | G09;
assign G05 = ~QB[4] & ~QB[3] & ~QB[2] & ~QB[1] & ~QB[0];
assign BSIN = ~Q01 ? 1’bz : 1’b0;
assign ASIN = ~Q00 ? 1’bz : 1’b0;
//PH_DRV----------------------------------------
DF F06 (.C(CLK), .D(G20), .R(G19), .S(0), .CE(1), .Q(A0));
DF F07 (.C(CLK), .D(~G20), .R(G19), .S(0), .CE(1), .Q(A1));
DF F08 (.C(CLK), .D(G22), .R(G19), .S(0), .CE(1), .Q(B0));
DF F09 (.C(CLK), .D(~G22), .R(G19), .S(0), .CE(1), .Q(B1));
DF F10 (.C(CLK), .D(G21), .R(G24), .S(0), .CE(1), .Q(Q10));
DF F11 (.C(CLK), .D(G23), .R(G24), .S(0), .CE(1), .Q(Q11));
assign G19 = ~RES | (STBY & (QB[7] | QB[6]));
assign G22 = Q11 ^ QC[1]; //assign G22 = Q11 ^ QD[1];
assign G23 = Q11 | ~BIN;
assign G20 = Q10 ^ G12;
assign G21 = Q10 | ~AIN;
//the rest of the main module code here:
endmodule
/////////////////////////////////////////////////////////////////////////////////-
module DF (D, C, CE, R, S, Q);
input D, C, CE, R, S;
output Q;
reg df;
always @(posedge C)
if ®
df <= 1’h0;
else if (S)
df <= 1’b1;
else if (CE)
df <= D;
assign Q = df;
endmodule
/////////////////////////////////////////////////////////////////////////////////-
module CB8R (C, R, Q);
input C, R;
output [7:0] Q;
reg [7:0] count;
always @(posedge C)
if ®
count <= 0;
else
count <= count + 1;
assign Q = count;
endmodule
/////////////////////////////////////////////////////////////////////////////////-
module CB2BRE (UD, R, CE, C, Q);
input UD, R, CE, C;
output [1:0] Q;
reg [1:0] u_d;
always @(posedge C)
if ®
u_d <= 0;
else if (CE)
if (UD) begin
u_d <= u_d + 1;
end
else begin
u_d <= u_d - 1;
end
assign Q = u_d;
endmodule
//////////////////////////////////////////////my add///////////////////////////////////-
module CB3BRE (UD, R, CE, C, Q);
input UD, R, CE, C;
output [2:0] Q;

reg [2:0] u_d;
always @(posedge C)
if ®
u_d <= 0;
else if (CE)
if (UD) begin
u_d <= u_d + 1;
end
else begin
u_d <= u_d - 1;
end
assign Q = u_d;
endmodule
////////////////////////////////////////corrected output [7:0]/////////////////////////////////////////-
module CB3RE (C, R, CE, Q);
input C, R, CE;
output [2:0] Q;
reg [2:0] count;
always @(posedge C)
if ®
count <= 0;
else if (CE)
count <= count + 1;
assign Q = count;
endmodule
/////////////////////////////////////////////////////////////////////////////////-

Вот это компилится Максом.

ага, пасиб, вижу что синтаксис чуть отличается, сейчас тоже в макс попробую засунуть

Анатолий, даже в самые отдаленные хутора пришла программируемая логика.
Пора начинать 😉

Пора начинать 😉

ну, то быстрее паяльник разогреет ? В)

Анатолий, даже в самые отдаленные хутора пришла программируемая логика.
Пора начинать 😉

Не, я сейчас все больше в Компасе - железяки пытаюсь изобретать, как ни противно это моей натуре.😁 Надеюсь, в январе что-нибудь начнут точить-фрезеровать, а я, тем временем, буду дальше грызть управляющую программу.
Так что до ПЛИС руки, боюсь, не скоро дойдут: нет у меня для них актуальной задачи, так чтобы без них - невмоготу.

Юрий, есть прогресс в моделировании?

Вот тут еще немножко теории как это сделано у Марисса.

Можете поделится кодом testbench для этого дела?

Что-то не могу разобраться как в ISE Project Navigator запускать симулятор (кажись wave называется).

Ткните пожалуйста пальцем куда смотреть надо и в какой последовательности.

луше сразу привыкайте к хорошему: Active HDL рулит.

луше сразу привыкайте к хорошему: Active HDL рулит.

Так вроде как и ModelsimXE с ISE работает без вопросов.

луше сразу привыкайте к хорошему: Active HDL рулит.

Cразу видно, человек КИТа начитался.

to mura
Юрий, так как насчет содержания моего поста

Юрий, есть прогресс в моделировании?

Вот тут еще немножко теории как это сделано у Марисса.

Можете поделится кодом testbench для этого дела?

Cкоро начну “боевые” испытания. А тесткод не писал, в МАКсе удобный симулятор, и там все задается графически.

Интерестно,как обстоят дела с драйвером…и подскажите boldive ,по Вашему мнению какой драйвер будет лучше: 1)на LS8290 или 2)на Xilinx CPLD

Разумеется на CPLD, только там код надо слегка до ума довести.